Conventional NAND flash memory systems use a large number of parallel signals for the commanding, addressing, and data transferring operations. This was a very popular way of configuring memory systems and results in very fast system operation. This is particularly true for random access memory devices like DRAM (dynamic random access memory), SRAM (static random access memory), etc.
A disadvantage arises from this approach in that a large number of parallel signal lines need to be routed to each and every memory device in the memory system. Also, the system power supply must have higher capacity in order to deliver higher peak power for parallel signaling. Write and read throughput for conventional NAND flash memory can be directly increased by using a higher operating frequency. For example, the present operating frequency of about 40 MHz (=25 ns for tRC in NAND Flash) can be increased to about 100˜200 MHz. While this approach appears to be straightforward, there is a significant problem with signal quality at such high frequencies, which sets a practical limitation on the operating frequency of the conventional NAND flash memory.
In particular, the conventional NAND flash memory communicates with other components using a set of parallel input/output (I/O) pins, numbering 8 or 16 depending on the desired word configuration, which receive command instructions, receive input data and provide output data. This is commonly known as a parallel interface. High speed operation will cause well known communication degrading effects such as cross-talk, signal skew and signal attenuation, for example, which degrades signal quality. Such parallel interfaces use a large number of pins to read and write data. As the number of input pins and wires increases, so do a number of undesired effects. These effects include inter-symbol interference, signal skew and cross talk.
In order to address some of these disadvantages, several serial-connected system configurations featuring a set of memory devices connected in a ring have been provided. These include ‘Multiple Independent Serial Link Memory’ (US20070076479A1), ‘Daisy Chain Cascading Devices’ (US20070109833A1), ‘Memory with Output Control’ (US20070153576A1), ‘Daisy chain cascade configuration recognition technique’ (US2007233903A1), and ‘Independent Link and Bank Selection’ (US2007143677A1), all of which are assigned to the same assignee as this application and are hereby incorporated by reference in their entirety. These systems typically have serial in/out data pins along with two control signals for the enabling and disabling of a serial input port and serial output port respectively in order to provide a memory controller with the maximum flexibility of serial data communication. Some of these memory system configurations employ a shared bus topology for the system clock distribution, which is referred to as a ‘common clock system’ or ‘multi-drop clocking system’. Some of these architectures use a point-to-point serial-connected clocking architecture featuring a DLL (delay locked loop) or PLL (phase locked loop) in every memory chip in order to synchronize two clock signals in each memory device, one being an input clock received from a preceding device or controller and the other being an output clock transmitted to the next device.